Video clock synthesizer 를 가진 2.7-/1.62-gbps displayport PHY 설계 = Design of 2.7-/1.62-gbps displayport PHY with video clock synthesizer
표제/저자사항
Video clock synthesizer 를 가진 2.7-/1.62-gbps displayport PHY 설계 = Design of 2.7-/1.62-gbps displayport PHY with video clock synthesizer / Won-SeokSeo